1. Field of the Disclosure
The present disclosure relates generally to integrated circuit devices and more particularly to vias for integrated circuit devices.
2. Description of the Related Art
An integrated circuit device typically includes vias to connect different metal layers of the integrated circuit device. The vias can have different shapes, surrounding metal area, and other characteristics that determine the reliability and manufacturability of the vias. A via design having a particularly high level of reliability and manufacturability is referred to as a design-for-manufacturability, or DFM, via. Typically, the greater the number of DFM vias in an integrated circuit device design, the greater the manufacturing yield and reliability of the integrated circuits resulting from the design.
It is typically desirable to include as many DFM vias in the integrated circuit device design as practical. However, because of design rule restrictions, layout issues, and other factors, DFM vias sometimes cannot be used in particular via locations of the integrated circuit device. Accordingly, during design of the integrated circuit device, a routing tool is sometimes used to identify via locations where DFM vias can be used. The routing tool is supplied with a plurality of via definitions, with each definition representing a different via design and associated DFM quality. At each via location, the routing tool attempts to use each via definition, and selects the definition that has the highest DFM quality and does not violate a routing rule or other design rule. The ability of the routing rule to improve the overall manufacturability of the integrated circuit device depends on the quality of the supplied via definitions. However, generation of the via definitions is typically done manually, consuming a large amount of time and engineering resources.